My 2001 Efforts:
http://www.ultratechnology.com/ml0.htm
His hardware was designed to support a simple approach to software and to be fast and cheap. The software was designed to be as simple and efficient as possible. While a couple of C compilers have been produced they have not included significant optimization. There remains much work to be done to integrate this technology to the larger world of standard development tools. Forth was made public domain long ago and there was a PD Forth community before the new Free Software community. The fact that these designs and the required software is so simple makes them ideal for Free Software projects.
Mr. Moore met John Sokol while doing a presentation for the Tech Startup Connection, formerly the Parallel Processing Connection, about these designs and his approach to VLSI CAD. Mr. Sokol, well known in the BSD community and as an Internet video pioneer, expressed interest in a new design for a cluster chip with multiple CPU and memory nodes connected via register based communication busses. Mr. Sokol brought the interest and expertise to support integration with conventional software tools and Enumera was formed.
25X a 63,000 MIP Parallel Multiple Stack Computer Cluster Chip for $1
The latest chip design is more difficult to describe because the outside of the chip, the action of the pins, is programmable. It can be programmed to mate directly to an 18-bit cache RAM without the need for a circuit board. It essentially uses the same CPU architecture and instruction set as F21 from a programmer's point of view with an increase of the instruction count to 29. But the layout of gates is quite different and new and Chuck is exploiting some new tricks to push the state of the art in hardware performance. In addition to being an asynchronous processor design this design also uses more dynamic logic and has a more high level description of the layout in colorforth source.
25X it is designed to be a very small chip that could be sold for about $1 in quantity. Small volume prototype runs are substantially more expensive. 25X contains 25 CPU core each with its own memory. They are connected to each other via internal communication busses and to the outside world via the pins. With 25 2400 Forth MIP CPU on a one dollar chip the metric is 63,000 MIPS per dollar of hardware. A production cluster chip could be larger than a one dollar chip for millions of MIPS but a tiny one with only 25 CPU can be prototyped more easily. As Mr. Moore said, "They are small. They don't do much, but they do it very fast." [Moore, 2002]
The chip could be programmed to act as other more conventional parts, as a single chip or be used as a node in a larger parallel computer. Like an FPGA or general purpose computer it is very difficult to describe exactly what the things you can make with it could do. 25X is more like an FPGA with 2400 MIP Forth engines as logic blocks than a typical desktop processor. I think the 25X design looks like most of a multi-line gigabit Internet router on a $1 chip, something that one would snap on the end of a fiber to connect it to other fibers or anything else.
Because these designs are simple at both an abstract and gate count requirement level they seem to be the little engine that can. These highly gate and code efficient designs can often be the most efficient way to perform the programmable functions in some device. They allow cheaper FPGA or cheaper custom VLSI part options for many mundane computing operations because they are small and run compact code and they simplify the task of programming. To become more mainstream these designs will require development tools and pre-packaged hardware devices with software libraries. As more people become aware of these technologies perhaps people in the Free Software community may find ways to integrate the technology.
Enumera website from 2001. Thank You archive.org.
https://web.archive.org/web/20010307063852/http://enumera.com/
2007
https://slashdot.org/story/07/08/20/1830221/mit-startup-unveils-new-64-core-cpu
It's was called Enumera www.enumera.com
I started to work with Chuck Moore, the author of the FORTH Language on a 7X7 array of very fast small processors.
From at talk I did, February 16, 2001
From http://www.dnull.com/~sokol/amorp/emtalk.ppt [dnull.com]
On this size Chip a 7x7 array (49 CPU's) with ram could be
build. Co-processors could also be added.
Each CPU's would be operating at 2400 MIPS x 49 for a total of 117 Billion operations per second.
The power consumption would be 1 watt 1.8 Volts a 500 mA.
With this level of computing power new applications that were unthinkable before, now become possible.
Also mention earlier on Slashdot:
http://developers.slashdot.org/comments.pl?sid=138 584&threshold=0&commentsort=0&mode=thread&cid=1160 0799 [slashdot.org]
And earlier here:
http://www.colorforth.com/ [colorforth.com] 25x Multicomputer Chip
This eventually became IntellaSys after Enumera failed.
IntellaSys CTO Chuck Moore to Present at In-Stat Spring Processor Forum; Scalable Embedded Array Platform for Implementing Asynchronous, Scalable Multicore Solutions Using Elegant VentureForth Programming to Be Discussed in Detail
http://www.intellasys.net/products/24c18/SEAforth- 24A-3.pdf [intellasys.net]
http://www.findarticles.com/p/articles/mi_m0EIN/is _2005_Oct_24/ai_n15730157 [findarticles.com]
http://www.findarticles.com/p/articles/mi_m0EIN/is _2006_May_1/ai_n16135032 [findarticles.com]
Also for older info see:
Specifically look at the P21 / I21/ F21 chips...
http://www.enumera.com/chip/ [enumera.com]
http://www.ultratechnology.com/ml0.htm [ultratechnology.com]
http://www.ultratechnology.com/f21.html#f21 [ultratechnology.com]
http://www.ultratechnology.com/store.htm#stamp [ultratechnology.com]
http://www.ultratechnology.com/cowboys.html#cm [ultratechnology.com]
